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integrated circuit systems, inc. ics9248-150 0352g?08/04/06 pin configuration 48-pin ssop and tssop recommended application: serverworks grand champion systems output features: 8 - differential cpu clock pairs @ 3.3v 1 - 3v 33mhz pci clocks 1 - 48mhz clock 1 - inverted 48mhz clock 1 - 14.318mhz reference output features: up to 200mhz frequency support support power management: power down mode supports spread spectrum modulation: 0 to -0.5% down spread. uses external 14.318mhz crystal select logic for differential swing control, test mode, tristate, power down, spread spectrum. external resistor for current reference fs pins for frequency select key specifications: ? pci output jitter <500ps cpu output jitter <150ps 48mhz output jitter <350ps ref output jitter < 1000ps frequency generator for multi-processor servers functionality 0 0 1 / 3 3 1 l e s0 s f1 s fn o i t c n u f 000 z h m 0 0 1 e v i t c a 001 e d o m t s e t z h m 0 0 1 010 e d o m t s e t z h m 0 0 1 011 s t u p t u o l l a e t a t s i r t 100 z h m 3 3 1 e v i t c a 101 e d o m t s e t z h m 3 3 1 110 z h m 0 0 2 e v i t c a 111 d e v r e s e r block diagram pciclk vdd48 fs0/48mhz fs1/48mhz# gnd48 vddcpu cpuclkt0 cpuclkc0 gndcpu cpuclkt1 cpuclkc1 vddcpu cpuclkt2 cpuclkc2 gndcpu cpuclkt3 cpuclkc3 vddcpu ref spread# gndref x1 x2 vddref sel100/133 gndpci vdda gnda pd# vddcpu cpuclkt4 cpuclkc4 gndcpu cpuclkt5 cpuclkc5 vddcpu cpuclkt6 cpuclkc6 gndcpu cpuclkt7 cpuclkc7 vddcpu multsel0 multsel1 gnd gndi ref i ref vddi ref ics9248-150 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 i ref pll2 pll1 spread spectrum 48mhz pciclk 48mhz# x1 x2 xtal osc cpu divder pci divder pd# spread# multsel(1:0) sel100/133 fs(1:0) control logic config. reg. ref 8 8 cpuclkt (7:0) cpuclkc (7:0) analog power groups vdd48, gnd48 = 48mhz, pll2 vdda=vdd (core supply voltage 3.3v) gnda=ground for core supply digital power group vddref, gndref = ref, xtal
2 ics9248-150 0352g?08/04/06 general description pin configuration ics9248-150 is a main clock for serverworks grand champion systems. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. ics9248-150 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. r e b m u n n i p e m a n n i pe p y tn o i t p i r c s e d 1k l c i c pt u ot u p t u o k c o l c i c p , 4 2 , 8 1 , 2 1 , 6 , 2 , 3 4 , 7 3 , 1 3 d d vr w py l p p u s r e w o p v 3 . 3 3 0 s fn in i p t c e l e s y c n e u q e r f z h m 8 4t u ot u p t u o k c o l c z h m 8 4 4 1 s fn in i p t c e l e s y c n e u q e r f # z h m 8 4t u ot u p t u o k c o l c z h m 8 4 d e t r e v n i , 8 2 , 1 2 , 5 1 , 9 , 5 7 4 , 0 4 , 4 3 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g , 6 1 , 2 4 , 9 3 , 6 3 , 3 3 7 , 0 1 , 3 1 ) 0 : 7 ( t k l c u p ct u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o , 7 1 , 1 4 , 8 3 , 5 3 , 2 3 8 , 1 1 , 4 1 ) 0 : 7 ( c k l c u p ct u o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o t n e r r u c e r a . s a i b e g a t l o v 9 1f e rt u oz h m 8 1 3 . 4 1 t u p t u o e c n e r e f e r 0 2# d a e r p sn i t s o h l a i t n e r e f f i d e h t n o y t i l a n o i t c n u f m u r t c e p s d a e r p s s e k o v n i w o l e v i t c a , s k c o l c 2 21 xt u p n i l a t s y r c 2 xt u p n i l a t s y r c z h m 8 1 3 . 4 1 3 22 xt u p t u o l a t s y r c 1 xt u p t u o l a t s y r c z h m 8 1 3 . 4 1 6 4 , 5 2 f e r i d d v , a d d v r w pv 3 . 3 y l p p u s r e w o p g o l a n a 6 2f e r it u o k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a s e k a t n i p s i h t . s r i a p . t n e r r u c d e r i u q e r e h t h s i l b a t s e o t r e d r o 0 3 , 9 2) 0 : 1 ( l e s t l u mn is t u p n i t c e l e s g n i w s u p c 4 4# d pn i. w o l e v i t c a . e d o m n w o d - r e w o p s e k o v n i 5 4 , 7 2 f e r i d n g a d n g r w py l p p u s v 3 . 3 r o f s n i p d n u o r g g o l a n a 8 43 3 1 / 0 0 1 l e sn iz h m 3 3 1 = h g i h , z h m 0 0 1 = w o l . t c e l e s y c n e u q e r f u p c
3 ics9248-150 0352g?08/04/06 truth table l e s 0 0 1 / 3 3 1 0 s f1 s f k l c u p c z h m k l c i c p z h m 8 4 z h m 000 0 0 13 38 4 001 0 0 13 3e l b a s i d 010 0 0 1e l b a s i de l b a s i d 011 e t a t s i r te t a t s i r te t a t s i r t 100 3 3 13 38 4 101 3 3 13 3e l b a s i d 110 0 0 23 38 4 111 2 / k l c t8 / k l c t2 / k l c t cpuclk buffer configuration s n o i t i d n o cn o i t a r u g i f n o cd a o ln i mx a m t u o i ) v 0 3 . 3 ( l a n i m o n = d d v f o s n o i t a n i b m o c l l a n w o h s r r d n a 1 m , 0 m w o l e b e l b a t n i r o f d a o l t s e t l a n i m o n n o i t a r u g i f n o c n e v i g % 7 -i l a n i m o n% 7 +i l a n i m o n t u o i % 5 0 3 . 3 = d d v f o s n o i t a n i b m o c l l a n w o h s r r d n a 1 m , 0 m w o l e b e l b a t n i r o f d a o l t s e t l a n i m o n n o i t a r u g i f n o c n e v i g % 2 1 -i l a n i m o n % 2 1 +i l a n i m o n
4 ics9248-150 0352g?08/04/06 0 l e s t l u m1 l e s t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i ) r r * 3 ( / d d v t u p t u o t n e r r u c , z @ h o v a m 2 3 . 2 = f e r i 00 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 6 @ v 1 7 . 0 00 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 5 @ v 9 5 . 0 01 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 6 2 / v 5 8 . 0 01 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 1 7 . 0 10 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 6 @ v 6 5 . 0 10 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 5 @ v 7 4 . 0 11 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 6 @ v 9 9 . 0 11 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 5 @ v 2 8 . 0 00 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 3 @ v 5 7 . 0 00 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 2 @ v 2 6 . 0 01 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 3 @ v 0 9 . 0 01 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 2 @ v 5 7 . 0 10 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ 0 6 . 0 10 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ v 5 . 0 11 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 3 @ v 5 0 . 1 11 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 2 @ v 4 8 . 0 cpuclk swing select functions
5 ics9248-150 0352g?08/04/06 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v d d -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 ma i il2 v in = 0 v; inputs with pull-up resistors -200 operating supply current i dd3. 3op c l = 0 pf; select @ 100 mhz 181 250 ma powerdown current i dd3. 3p d c l = 0 pf; input address to vdd or gnd 52 60 ma input frequency f i v d d = 3.3 v 14.318 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf cpu freq. = 100/133 mhz 8 ms cpu freq. = 200 mhz 10.5 ms cpu freq. = 100/133 mhz 8 ms cpu freq. = 200 mhz 10.5 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. 2 from vdd = 3.3v to 1% of target frequency 3 from deassertion of pd# to 1% of target frequency delay 1 input capacitance 1 input low current clk stabilization 1, 2 clk recovery 1, 3 t stab t rec
6 ics9248-150 0352g?08/04/06 electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 14.318 mhz output impedance r dsp1 1 v o = v d d *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.6 4 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2.4 4 ns duty cycle d t1 1 v t = 1.5 v 45 53.5 55 % skew t sk1 1 v t = 1.5 v n/a ps jitter t jcyc-cyc 1 v t = 1.5 v 305 1000 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 770 850 1 voltage low vlow -150 5 150 1 max voltage vovs 756 1150 1 min voltage vuds -300 -7 1 rise time t r2b 1 v ol = 20%, v oh = 80% 175 324 700 ps 1 fall time t f2b 1 v oh = 80%, v ol = 20% 175 501 700 ps 1 diff. crossover volt a v x v dd = 3.3v 45 50 55 % 1 duty cycle d t2b 1 v t = 50% 45 51.2 55 %1 skew cput0:7 t sk2b 1 v t = 50% 83.8 100 ps 1 skew cpu c0:7 t sk2b 1 v t = 50% 78.5 100 ps 1 jitter t jcyc-cyc 1 v t = 50% 86 150 ps 1 1 guaranteed by design, not 100% tested in production. 2 i owt can be varied and is selectable thru the multsel pin. measurement on single ended signal using absolute value. mv statistical measurement on single ended signal using oscilloscope math function. mv
7 ics9248-150 0352g?08/04/06 electrical characteristics - pci t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 33.3 mhz output impedance r dsp1 1 v o = v d d *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.2 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.2 2 ns duty cycle d t1 1 v t = 1.5 v 45 49.9 55 % skew t sk1 1 v t = 1.5 v n/a ps jitter t jcyc-cyc 1 v t = 1.5 v 139.7 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48mhz t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 48 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.3 4 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.6 4 ns duty cycle d t1 1 v t = 1.5 v 45 52.5 55 % skew t sk1 1 v t = 1.5 v n/a ps jitter t jcyc-cyc 1 v t = 1.5 v 175 350 ps 1 guaranteed by desi g n, not 100% tested in production.
8 ics9248-150 0352g?08/04/06 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power down latency should be as short as possible but conforming to the sequence requirements shown below. notes: 1. as shown, the outputs stop low on the next falling edge after pd# goes low. 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 3. the shaded sections on the vco and the crystal signals indicate an active clock. cpuclkt cpuclkc vco crystal pd#
9 ics9248-150 0352g?08/04/06 ordering information ics9248 y f-150ln-t designation for tape and reel packaging lead free, rohs compliant pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y f - ppp ln - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n
10 ics9248-150 0352g?08/04/06 ordering information ics9248 y g-150ln-t designation for tape and reel packaging lead free, rohs compliant pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y g - ppp ln - t in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b0.170.27.007.011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l0.450.75.018.030 n
11 ics9248-150 0352g?08/04/06 revision history rev. issue date description page # e 6/9/2005 removed pci skew from electrical characteristics table. 7 f 3/29/2006 updated electrical characteristics cpu table. 6 g 8/4/2006 added ln to ordering information. 9-10
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